This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-214326 filed on Jul. 23, 2002; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor integrated circuit, particularly, a flip-flop circuit.
FIGS. 1A and 1B show a known flip-flop circuit. In detail, FIG. 1A and FIG. 1B show a signal-transfer circuit and a clock-supply circuit, respectively, of the known flip-flop circuit.
The signal-transfer circuit has a first clocked inverter INV21, the input node thereof being connected to an input D; a first inverter INV22 connected in series to the output node of the first clocked inverter INV21; a second clocked inverter INV23 interconnected with the first inverter INV22; a transmission gate TG21 connected in series to the output node of the first inverter INV22; a second inverter INV24 connected in series to the output node of the transmission gate TG21; a third clocked inverter INV25 interconnected with the second inverter INV24; and a third inverter INV26 connected in series to the output node of the second inverter INV24, the output of the third inverter INV26 being connected to an output Q.
The clock-supply circuit has a fourth inverter INV27, the input node thereof being connected to a supply node for a clock signal CLK and a fifth inverter INV28 connected in series to the output node of the fourth inverter INV27. An internal clock signal CKI is generated at the output node of the fifth inverter INV28 and an inverted internal clock signal CKIB is generated at the output node of the fourth inverter INV27.
The internal clock signal CKI is supplied to N-channel MOS transistors of the second clocked inverter INV23 and the transmission gate TG21 and also P-channel MOS transistors of the first and the third clocked inverters INV21 and INV25. The inverted internal clock signal CKIB is supplied to N-channel MOS transistors of the first and the third clocked inverters INV21 and INV25 and also P-channel MOS transistors of the second clocked inverter INV23 and the transmission gate TG21.
Shown in FIGS. 1A and 1B are the internal clock and inverted clock signals supplied only to the N-channel MOS transistors for brevity.
A low-level clock signal CLK causes generation of a low-level internal clock signal CKI and a high-level inverted internal clock signal CKIB. On the contrary, a high-level clock signal CLK causes generation of a high-level internal clock signal CKI and a low-level inverted internal clock signal CKIB.
An input signal supplied via the input D is supplied to the first inverter INV22 via the first clocked inverter INV21 when the clock signal CLK is at a low level, or the inverted clock signal CKBI at a high level. The input signal supplied to the first inverter INV22 is inhibited from being output therefrom because the transmission gate TG21 and the second clocked inverter INV23 have been turned of f by the low-level internal clock signal CKI.
On switching from the low to high level for the clock signal CLK, the first clocked inverter INV21 is turned off whereas the transmission gate TG21 and the second clocked inverter INV23 is turned on. Therefore, on switching of the clock signal CLK, the input signal supplied via the input D is held by the first inverter INV22 and the second clocked inverter INV23 and further output from the output Q through the transmission gate TG21 and the second and the third inverters INV24 and INV26.
Next, on switching from the high to low level for the clock signal CLK, the transmission gate TG21 is turned off whereas the third clocked inverter INV25 is turned on. Therefore, on switching of the clock signal CLK, the input signal passed through the transmission gate TG21 is held by the second inverter INV24 and the third clocked inverter INV25 and further output from the output Q through the third inverter INV26. This signal-transfer state continues until the transmission gate TG21 is turned on again to receive another level of signal.
Any skilled in the art knows that flip-flop circuits consume much power in a large-scale integrated circuit (LSI).
The known flip-flop circuit shown in FIGS. 1A and 1B is charged and discharged at several nodes in accordance with operations based on the clock signal CLK, thus consuming power. Twelve transistors are charged and discharged among 24 transistors in total, for example, for the flip-flop circuit shown in FIGS. 1A and 1B, thus consuming power even if the input-signal level via the input D does not vary, which is about 40% of power consumed when the signal level varies.
The inventors Hamada et al. disclose a low-power-consuming flip-flop circuit in Japanese Unexamined Patent Publication No. 10-240713 corresponding to U.S. Pat. No. 6,204,707.
FIG. 2 shows a circuit block diagram of the disclosed flip-flop circuit.
The low-power-consuming flip-flop circuit has a first inverter INV41, the input node thereof being connected to an input D; a transmission gate TG31 connected in series to the output node of the first inverter INV41; a second inverter INV42 connected in series to the output node of the transmission gate TG31; a first clocked inverter INV43 interconnected with the second inverter INV42; and a third inverter INV44 connected in series to the output node of the transmission gate TG31, the output of the third inverter INV44 being connected to an output Q.
The first and the second inverters INV41 and INV42 and the first clocked inverter INV43 and also the transmission gate TG31 constitute a latch as a signal-transfer circuit. An output Q is generated at the output node of the third inverter INV44 for steady signal supply, although it can be generated at the output node of the second inverter INV42.
The low-power-consuming flip-flop circuit also has a pair of a first N-channel MOS transistor NM21 and a first P-channel MOS transistor PM21 connected in parallel, the drain of the MOS transistor NM21 and also the source of the MOS transistor PM21 being connected to the output node of the transmission gate TG31, the gate of the MOS transistor NM21 being connected to the output node of the first inverter INV41, the gate of the MOS transistor PM21 being connected to the input D; and another pair of a second N-channel MOS transistor NM22 and a second P-channel MOS transistor PM22 connected in parallel, the drain of the MOS transistor NM22 and also the source of the MOS transistor PM22 being connected to the output node of the second inverter INV42, the gate of the MOS transistor NM22 being connected to the input D, the gate of the MOS transistor PM22 being connected to the output node of the first inverter INV41.
The pair of the first N-channel MOS transistor NM21 and the first P-channel MOS transistor PM21 and the other pair of the second N-channel MOS transistor NM22 and the second P-channel MOS transistor PM22 constitute an EX-NOR logic circuit EX-NOR3 for an exclusive-NOR operation to the D- and Q-inputs.
Moreover, the low-power-consuming flip-flop circuit has a 2-input AND logic circuit AND21, a clock signal CK being supplied to one of the inputs thereof; a 2-input NOR logic circuit NOR21, connected to one of the inputs thereof being the source of the first N-channel MOS transistor NM21, the drain of the first P-channel MOS transistor PM21, the source of the second N-channel MOS transistor NM22 and the drain of the second P-channel MOS transistor PM22, connected to the other input of the 2-input NOR logic circuit NOR 21 being the output node of the AND logic circuit AND21; a 2-input NAND logic circuit NAND21, the clock signal CLK being supplied to one of the inputs thereof, connected to the other input thereof being the output node of the NOR logic circuit NOR21; a fourth inverter INV45, connected to the input thereof being the output node of the NOR logic circuit NOR21, the output node thereof being connected to the other input of the AND logic circuit AND21; and a fifth inverter INV46 connected in series to the output node of the NAND logic circuit NAND21, constituting a clock-control circuit CLK-CTRL3.
An internal clock signal CKI is generated at the output node of the fifth inverter INV46 and an inverted internal clock signal CKIB is generated at the output node of the NAND logic circuit NAND21.
The internal clock signal CKI is supplied to N-channel MOS transistors of the transmission gate TG31 and also P-channel MOS transistors of the first clocked inverter INV43. The inverted internal clock signal CKIB is supplied to N-channel MOS transistors of the first clocked inverter INV43 and also P-channel MOS transistors of the transmission gate TG31.
Shown in FIG. 2 are the internal clock and inverted clock signals supplied only to the N-channel MOS transistors for brevity.
In the low-power-consuming flip-flop circuit shown in FIG. 2, the EX-NOR logic circuit EX-NOR3 compares the input D and the output Q to generate a logic signal indicating a logic value in accordance with the result of the comparison, for control over the clock-control circuit CLK-CTRL3. The internal clock and inverted internal clock signals CKI and CKIB derived from the clock signal CLK are supplied to the signal-transfer circuit only when the input D is different from the output Q in logic value, for low power consumption.
The low-power-consuming flip-flop circuit shown in FIG. 2 has a single latch with a limited number of transistors as the signal-transfer circuit, however, includes a large number of transistors for the clock-control circuit CLK-CTRL3.
A semiconductor integrated circuit according to one embodiment of the present invention comprises:
a first latch to pass or store a signal in accordance with a logic value of a first internal clock signal;
a second latch connected in series to the first latch, to store or pass a signal in accordance with a logic value of a second internal clock signal, with operational characteristics which is an inversion of operational characteristics of the first latch;
a first comparator to compare signal logic values at signal-input and -output nodes of the first latch;
a second comparator to compare signal logic values at signal-input and -output nodes of the second latch;
a first clock controller to generate a signal having a specific logic value for storing the signal when the signal-input and -output nodes of the first latch have a specific same signal logic value whereas generate a specific clock signal when the signal-input and -output nodes of the first latch have different signal logic values, as the first internal clock signal, under a result of comparison by the first comparator; and
a second clock controller to generate a signal having a specific logic value for storing the signal when the signal-input and -output nodes of the second latch have a specific same signal logic value whereas generate the specific clock signal when the signal-input and -output nodes of the second latch have different signal logic values, as the second internal clock signal, under a result of comparison by the second comparator.
A semiconductor integrated circuit according to one detailed embodiment of the present invention comprises:
a first latch having a clock-input node, an input node connected to an input D and an output node connected to a node X, to pass a signal while a first internal clock signal supplied to the clock-input node is being at a first level whereas store the signal while the first internal clock signal is being at a second level;
a second latch having a clock-input node, an input node connected to the node X and an output node connected to an output Q, to pass a signal while a second internal clock signal supplied to the clock-input node is being at the second level whereas store the signal while the second internal clock signal is being at the first level;
a first comparator having an input receiving the input D and another input connected to the node X;
a first clock controller having an input connected to an output node of the first comparator and another input receiving a specific clock signal, to generate the first internal clock signal;
a second comparator having an input connected to the node X and another input receiving the output Q; and a second clock controller having an input connected to an output node of the second comparator and another input receiving the specific clock signal, to generate the second internal clock signal.